perm filename XXX[P,JRA]2 blob
sn#134876 filedate 1974-12-09 generic text, type C, neo UTF8
COMMENT ⊗ VALID 00010 PAGES
C REC PAGE DESCRIPTION
C00001 00001
C00002 00002 INTRODUCTION
C00005 00003 GENERAL DESCRIPTION
C00018 00004 FIGURE 1-1
C00022 00005 OPERATION AND PROGRAMMING
C00033 00006 PROCESSOR
C00036 00007 DESCRIPTION OF REGISTERS
C00043 00008 LOGIC DESCRIPTION
C00065 00009 ROM OUTPUT | SIGNAL DERIVED |PURPOSE
C00069 00010 ROM outputs ROM OUT(3:1) are decoded by a 74s138. The
C00084 ENDMK
C⊗;
INTRODUCTION
The Panofsky Map is a hardware option designed for use with the
PDP-11/45 Programmed Data Processor. This manual:
Provides an understanding of the Panofsky Map in a
PDP-11/45 system.
Explains the map hardware and how it can be used to
develop the memory management module of a software
operating system
Describes the map logic in sufficient detail to enable
maintenance personnel to perform on-site
troubleshooting and repair.
The map interacts with the KB11A Central Processor Unit and operating
system software to achieve PDP-11/45 system memory management
objectives. For this reason, a description of memory management
system objectives and programming information is included in this
manual.
Chapter 1 introduces the purpose and features of the memory
management unit.
Chapter 2 describes the implementation of the features from a
programming level. It also describes the internal registers and
their application, hints, and exceptions of interest to programmers.
Chapter 3 provides a detailed description of the logic. The content
and organization of this chapter are based on the block schematics
contained in the prints.
Detailed descriptions of the processor, console, Unibus, Fastbus,
and memory logic that interface with the map are provided in the
following related documents.
PDP-1/45 System Maintenance Manual DEC-11-H45B-D
KB11-A Central Processor Unit Maintence Manual DEC-11-HKBB-D
MS11 Semiconductor Memory Systems Maintenance Manual DEC-11-HMSB-D
PDP-11/45 Processor Handbook 112.01071.1876
PDP-11 Unibus Interface Manual (2nd Edition) DEC-11-HIAB-D
GENERAL DESCRIPTION
CHAPTER 1
This chapter describes the features of the Panofsky Map in "systems"
terms and also includes a specification summary.
PURPOSE
The Map intercepts addresses generated by the processor
(before they reach memory), processes the addresses received, and
then transmits the processed addresses to memory. Address processing
is the main function of the memory management option. This
processing of modification of addresses is called "mapping".
Processing is mapping because it consists of mapping small parts of
address space into arbitrary physical locations of a larger memory.
The location of the Map in the PDP-11/45 system is shown in Figure
1-1.
PREREQUISITE
A memory management unit of some sort is required on all
systems with more than 28K of main memory (bipolar, MOS, and core).
The option should also be considered for systems with real-time and
timesharing applications as well as any system that runs user
programs under a control or monitor program. For a narrative
description of the PDP-11/45 system's ability to support timesharing
and real-time operating systems, refer to Paragraph 4.3 in the KB11A
Central Processor Maintenance Manual. The advantages of the Panofsky
Map over the DEC KT11-C lie in the facts that it is a real map, not
just a relocation box and that it allows up to
.5 megaword of physical addressing space.
FEATURES
Expands the basic 28K word memory capability to 512K words.
Provides dynamic read-only and execute-only memory protection
Provides up to 4 separate maps enabling separate address
spaces for the Kernel,Supervisor, and User modes.
Allows up to 64 pages, utilizing 100% of the virtual address
space.
Provides additional advanced memory management capabilities.
MEMORY PROTECTION
The memory management unit enables the user to protect one
section of memory from access or destruction by programs located in
another section. The map divides the memory into sections called
pages. Each individual page has a protection or access key
associated with it that restricts access to the page. With the
memory management unit, a page can be keyed invalid (memory neither
readable nor writable), read-only (no write or store operations to
memory), write only (only write or store operations to memory - not
too useful, but general), execute only (only instructions, immediate
operands, absolute addresses, and index words can be accessed from
memory), and unlimited access. These types of protection in
association with other features of the map enable the user to develop
an ultrareliable computer operating system. With the invalid key,
memory not specifically assigned to a program can be made unavailable
to it. As a result, program errors cannot modify any other programs.
The read only key protects data bases and pure code sections from
malicious or accidental destruction while allowing them to be
accessed. With User mode programs, the execute-only feature allows
proprietary code to be executed but not copied.
MAPPING/VIRTUAL MEMORY
Often it is desirable to load a program into one set of
locations in memory and then execute it as if it were located in
another set of locations, e.g., when several user programs are
simultaneously stored in memory. When any one program is running, it
must be accessed by the processor as if it were located in the set of
addresses beginning at 0. When the processer accesses program
location 0, a page address is substituted for the high-order bits of
the address thus, the mapped location 0 of the program is accessed.
This same process is used for all references while the program is
running. A different set of page addresses is used for each of the
other programs in memory.
Processor-generated addresses differ from those that address
memory, thus the processor addresses are sometimes termed virtual
addresses, and the memory addresses termed physical addresses. The
memory management option specifies each page separately in a page
table, which allows a large program to be loaded into discontiguous
pages in memory. This ability eliminates the need to shuffle
programs to accomodate a new one. It also minimizes unusable memory
fragments, allowing more users to be loaded in a specific memory
size.
In timesharing systems with swapping, mapping eliminates the
need to relink a program when it is swapped into a different memory
location.
MEMORY EXPANSION
The mapped address is a 20-bit address that can access 512K
words of address space, enabling the memory management option to
expand the accessible address space of the procesor from 32K words to
512K words. Expanding the address space permits larger programs to be
handled and allows several programs to occupy the memory at once. In
addition, the map option provides for expansion into multiprocessor
systems where typically the total memory exceeds 28K words.
VARIABLE NUMBER OF PAGES
A program and its data may occupy as many as 128 pages in the
memory, 64K of instruction space and 64K of data space. This feature
enables small areas in memory to be protected, i.e., stacks, buffers,
etc. and the small size of the pages (512 words) results in a minimum
of page fragmentation problems. Associated with a program are two
page tables. Each page table has a variable number of pages (up to
64), controled by the Maximum Virtual Page register. If a reference
is made do a page exceeding this register, the cycle i aborted.
PAGE STATE INFORMATION
The memory map provides two bits of active page state
information: an "accessed" bit and a "written into" bit. These bits
are read by the operating system and indicate whether the page has
been accessed and, if so, whether it was written into. The accessed
bit is used with operating system programs to determine which page
should be overlaid with the new program page in systems that swap
programs back and forth from a disk. The written into bit is used to
determine whether the page to be overlaid must be swapped back to the
disk or whether it is identical to a copy already there.
INSTRUCTION/DATA SPACES
The mapping box can map data and instructions references with
separate page tables; thus, it is possible to have a user program of
64K words consisting of 32K pure program and 32K of data. Morever, a
convenient means of building reentrant shared programs is provided
(these programs keep a separate data area for each user). "Execute
only" protection is also provided. With this form of protection,
alterable data is automatically separated from reentrant code, and it
is impossible to read,das data, any information mapped as an
instruction.
KERNEL/SUPERVISER/USER SPACES
The map provides three sets of maps for use in the
processor's Kernel, Supervisor, and User modes. These sets of pages
increase system protection by physically isolating User programs from
service programs and both from the operating system. The three
spaces allow parallel processing of User, Supervisor, and Kernel
programs without fear of core conflicts.
FAULT RECOVERY
Three status registers record all information necessary to
recover from a page fault. This information comprises the page
number that faulted, the type of violation that caused the fault and
all information needed to easily restart the failing instruction once
the offending address has been made resident in memory.
FIGURE 1-1
______ ______ _____
________ | | | | | |
| | |MEMORY| | I/O | | I/O |
| | | | | DEV | | DEV |
| | C C |______| |______| |_____|
| |←-----------------→| ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
| | D D | |A|C|D |A|C|D |A|C|D
| |←------------------|____|_↓_↓_____|_↓_↓_____|_↓_↓______\
| | D | UNIBUS \
| | /--------------→|___________________________________ /
| | | A | | ↑ ↑ /
| | | /-→| | | |
| | | | |A |C |D
| | | | _↓__↓__↓___
| | | | A | |
| | | |--------→| |
| KB11A | C | | C | | A ___________
| |←--+------------+--------→| |←----| |
| | D | | D |SEMICONDUCT| C | OTHER |
| |←--+------------+---------| MEMORY |←---→| PROCESSOR |
| P | | | D | | D | |
| C R | |------------+--------→| |←---→|___________|
| E O | | D ______ | |___________|
| N C | D |--→| | | ↑ ↑ ↑
| T E |---| D | |A| |A |C |D
| R S |←--+---| |-/ _|__↓__↓___
| A S | A | A |MEMORY| | |
| L O |---+--→| MAP | | OTHER |
| R | C | C | | | PROCESSOR |
| |←--+--→|______| |___________|
| | |
| | | D ____________
| | \------→| | A = ADDRESS PATH
| | D | FP11 | D = DATA PATH
| |←----------| FLOATING | C = CONTROL SIGNALS
| | C | POINT |
| |←---------→| PROCESSOR |
| | |____________|
|________|
OPERATION AND PROGRAMMING
CHAPTER 2
BASIC MECHANISIMS
ADDRESS MAPPING MECHANISM
The current processor mode (Kernel, Supervisor, User) bits
(bits 14 and 15 of the processor status word) select one of three
sets of two registers. These registers select which of the 4 page
tables is to be used for instructions and which for data. All
instructions, index words, absolute addresses, and immediate operands
use the instruction page table. All other references use the data
page table. Bits 15 through 10 of the processor address are then
used as a 6 bit address into the selected page table. The data
contained in that address of the page table is an 8 bit (expandable
to 11 bits) physical page number. That 8 bit number is combined with
the 10 low order bits of the processor address to generate the
physical address that is sent out on the buses. Also contained in
the page table entry is a bit specifying whether this page is on the
Unibus or on the Fastbus.
Although the program appears to be in contiguous address
space to the processor, the 32K word virtual address space is
actually relocated to several separate areas of physical memory. As
long as the total available physical memory space is adequate, a
program can be loaded. The physical memory space need not be
contiguous.
Each page is mapped independently. There is no reason that
two or more virtual pages cannot be mapped to the same physical
address space. Also, the same page table can be selected for two or
more segments (i.e. instruction space of User mode and data space of
Supervisor mode). In fact, the normal usage would have the same page
table selected for instructions and data for each mode unless a
shared program or "execute only" operation was being implemented.
MEMORY PROTECTION MECHANISMS
Each page entry in each of the page tables has memory
protection bits associated with it. After the page selection occurs,
the type of reference is checked against the protection bits and if
the reference is found to be illegal, the transfer is aborted, the
processor is forced to Kernel D space 250.
When the protection bits are 0, the page is defined as non
resident and all references are aborted. A protection of 1 permits
reading but not writing. 2 gives write permission but not read (see
applications notes on Signetics 25120 for possible uses). 3 gives
full read/write access.
EXECUTE ONLY PROTECTION
The execute only type of memory protection is part of an
overall ability to use reentrant software, which prevents excessive
use of memory space when a program is provided for several users.
Such programs can be written in two parts. One part contains pure
code that is not modified during execution and can be used to
simultaneously service any number of users. A separate second part
of the program belongs strictly to each user and consists of the code
and data that is developed during the execution of the program.
Execute only memory protection can be implemented by mapping
the pure portion of the code with a page table associated with user
instruction space and protected to read only. The data section is
mapped with another page table that permits reading and writing.
Since individual pages can be protected individually, the program can
transfer from pure code of a common program to special code that is
user modifiable by merely jumping to another area of memory that is
not protected. The protected and unprotected parts of the code can
be widely separated in physical memory, but have close virtual
addresses. Also another user's map can use the same program and
share the pure part and have an unprotected area all its own. Of
course it is possible (and perhaps useful) to let programs share
pages that are not read only.
MAXIMUM VIRTUAL PAGE
Associated with each space (instruction and data) is a
maximum virtual page register. This feature allows the system to
fill only that part of the page table that is available to the user
and to leave the rest. All references to virtual pages greater than
the number loaded into this register are aborted.
MAPPED/TRANSPARENT
Associated with each space is a TRANSPARENT bit. When this
bit is on, all references to that space are unmapped and the physical
address is the same as the virtual address. All cycles are assumed to
be Unibus transactions, and the Fastbus is disabled. This feature
allows programs to have complete control of all devices connected to
the machine and of the processor itself. In transparent mode all
references with virtual address bits 15 and 14 on, will also have
bits 16 and 17 asserted automatically to address the high 8K of
Unibus address for device registers. No protection is provided
except for maximum virtual page violations.
PAGE STATE
A timeshared system swaps programs or parts of programs in
and out of memory using secondary storage facilities such as disk or
drum systems. In a swapping environment, the operating system must
provide the software routines that decide what programs should be
swapped and when an how these programs can be swapped between memory
and secondary storage. The operating system may have to decide which
active page is least likely to be required in the immediate future
and may therefore be swapped to make memory space available for a new
program. To allow the system to make such memory management
decisions, the map provides two status bits associated with each page
of each page table. An access updates the status bits in the entry
in the page table. WARNING: only the page entry used is updated;
other entries may point to that physical page, but they are not
updated. The ACCESSED bit indicates that a cycle has been taken to
that page. The WRITTEN INTO bit is turned on when a write cycle is
done. These bits may be set when the page table is first loaded if
the system has some reason to preload them.
ABORT MECHANISM
Memory references that violate the protection bits cause an
interrupt in the processor. The interrupt process is described in
Paragraph 5.3 of the PDP-11/45 Handbook. In memory map aborts, the
new PC for the abort service routine is taken from location 250 in
Kernel virtual D space while the new PS word is taken from 252. No
other interrupts use 250 as a trap vector. Aborted memory references
cause an interrupt before that cycle begins and do not complete the
reference.
PROCESSOR
MODE,I/D
|
___↓____
| map |
| space |
| table | PROCESSOR
|________| VIRTUAL ADDRESS
| |
____↓____________ ___________↓______
|9 8| 7 | |15 10|9 0|
|page table|trans-| | virtual |offset|
| number |parent| |page number| |
|__________|______| |___________|______|
| | | |
| \----------------------------+--------+---\
| /-------------------------/ | |
| | | |
____↓___________↓_____ | |
|7 6|5 0| | |
|page table| virtual |page table | |
| number |page number| address | |
|__________|___________| | |
| | |
| ______________ | |
| | page | | |
\-→| tables |--\ | |
| | | | |
|______________| | | |
| | |
______↓_____________ | |
| 11 |10 0| | |
page table|Unibus|physical page| | |
entry | | number | | |
|______|_____________| | |
| | | |
| | | |
| _____↓___________↓__ |
| |20 10|9 0||
| |physical page|offset||
| | number | ||
| |_____________|______||
| | |
| | |
| ___↓___ |
| | | |
\---------→|control|←------/
|_______|
|
|
/--------------------\
| |
_______↓________ ____↓___
|17 16|15 0| |20 0|
|special|physical| |physical|
| * | address| | address|
|_______|________| |________|
| |
* High order bits of | |
Unibus address on if ↓ ↓
transparent and 15,14=1 UNIBUS ADDRESS FASTBUS ADDRESS
DESCRIPTION OF REGISTERS
MAP REGISTERS
MAP SPACE TABLE
The map space table has 6 entries, one for each instruction
and data space of Kernel, Supervisor and User modes. The format is
as follows:
____________________________________________
|15 10|9 8| 7 |6 1| 0 |
|unused|page table|trans-|max virtual|spare|
| | number |parent| page | |
|______|__________|______|___________|_____|
The page table number indicates which of the four page tables
is to be used for this space.
The transparent bit causes all references in this space to be
unmapped. The physical address is the same as the virtual address.
Bits 17 and 16 are asserted if bits 15 and 14 are on in the virtual
address. All transfers are to the Unibus and the Fastbus is
disabled.
The maximum virtual page field indicates the maximum page
that may be referenced in this space. All greater numbered page
references are aborted.
PAGE TABLE ENTRIES
Each of the 4 page tables has 64 entries, one for each
virtual page. The format of the page table entries is as follows:
_____________________________________________________
| 15 | 14 | 13 | 12 | 11 |10 0|
|written|accessed|write | read |Unibus|physical page|
| into | |permit|permit| | number |
|_______|________|______|______|______|_____________|
The written into bit indicates that this page has been
written into by a reference to this entry.
The accessed bit indicates that this page has been accessed
by a reference to this entry.
Write permit allows write cycles to this page.
Read permit allows read cycles to this page.
When the Unibus bit is on, all references through this entry
address the Unibus only. When off, all references go to the Fastbus
only.
The physical page number field contains the high order
address bits of the physical page that will be addressed when the
virtual address selects this page table entry.
STATUS REGISTERS
STATUS REGISTER 0
Status register 0 is the basic control register of the map.
It allows the processer to turn mapping on and off, and indicates the
type of error causing an abort. The format of status register 0 is
as follows:
_______________________________________________________________________
| 15 | 14 | 13 | 12 |11 5|4 3| 2 |1 0|
|enable |max page |read permit|write permit|unused| pc |error in|error|
|mapping|violation| violation | violation | |mode| I space| mode|
|_______|_________|___________|____________|______|____|________|_____|
Unless the enable mapping bit is on all references will be
unmapped causing physical addresses to be equal to virtual addresses.
No Fastbus transfers will be done. This bit is reset when a RESET
instruction is executed and when front panel reset is done.
The max page violation bit is set when a reference is
attempted that exceeds the max page register for that space.
The read permit violation bit is set when a read cycle is
attempted from a page without the read permit bit.
The write permit violation bit is set when a write cycle is
attempted from a page without the write permit bit.
The pc mode field indicates the processor mode (bits 14 and
13 of the PSW) at the time of the error.
The error in I space bit indicates the type of space being
accessed at the time of the error (0 = D space, 1 = I space).
The error mode field indicates the actual processor mode of
the error access attempt. This may be different than the pc mode if
the current instruction is a MFPD, MFPI, MTPD, or MTPI.
STATUS REGISTER 1
Status register 1 contains the full virtual address of the
attempted access. This is loaded with the virtual address whenever a
cycle is attempted unless one of the error bits is on in status
register 0. As soon as those bits are cleared, register 1 will be
clobbered.
STATUS REGISTER 2
Status register 2 contains the address of the first word of
the instruction being executed when the abort occured. This is
loaded with the virtual address whenever the instruction register is
loaded unless one of the error bits is on in status register 0. As
soon as those bits are cleared, register 2 will be clobbered.
LOGIC DESCRIPTION
INTRODUCTION
In the PDP-11/45 system the Mapping Box is located between
the KB11A Central Processor Unibus and the Fastbus, and `nibus A
address lines (see block diagram). The processor provides a 16-bit
virtual memory address to the mapping box on the BAMX(15:00)H lines.
These lines permit addressing a maximum of 32K word locations. The
memory mapping box takes the high order 6 bits of the address to
examine a location in one of 4 Page Tables. the data contained in
that location (called a page table entry) supplies the high order
part of the physical address, with the low order 10 bits of the
virtual address tacked onto the bottom.
The physical address is provided in two versions. The 18 low
order bits are put on the Unibus A address lines, BUS A(17:00)L. In
addition, the 18 bit memory address formed by linking physical
address bits PA(20:06)H and virtual address bits BAMX(05:00)H is
output to the Fastbus; the high-speed Semiconductor Memory System is
connected to the Fastbus. Also supplied by the page table entry is a
bit indicating that this bit is for the Unibus or the Semiconductor
Memory. If it is a Unibus address, a signal is sent to the
Semiconductor Memory interface telling it not to respond. If the
address is intended only for the Semiconductor Memory, a signal is
sent to the processor, telling it that a Fastbus cycle is in
progress, and bits 16 and 17 of the Physical address that is used
internalally, are forced off so no internal registers will respond.
Specific addresses are assigned to the internal Page Table
Registers so that page table entries can be written into these
registers under program control. The data inputs from the processor
are BR(15:00)B L. These also provide data inputs to Status Register
0. The contents of the page tables and the status registers can be
read onto the processor internal data bus lines BUS INTD(15:00)L
under program control.
PAGE TABLES
Refer to the block diagram and drawings SAPA and SAPB. Four
separate 64 entry page tables are implemented in a 256 word memory
made of 256X1 chips. Each page entry is 16 bits and contains all the
information required to describe and locate a current active memory
page.
There are two ways to address one of the page table entries:
1. Virtual Memory Addressing: The high order 6 bits of the virtual
address are used to select which entry of a particular page table is
selected. The output of the Map Space Table (which will be described
later) selects which page table (quadrant of the memory) is selected.
2. Internal Trgister Addressing: When data is to be written into, or
read from a specific entry of the page tables, the 9 low order bits
of the internal register address are used to generate address bits PT
ADDR(7:0) and a "byte" select bit.
These two addresses are selected by a two way multiplexor depending
on the signal SSRL INT REG L which indicates that the physical
address is selecting the page tables' address range.
Data from the internal bus will be written into the page
tables when the following conditions are true: 1. TMCE C1 H -
Asserted for all DATAOx bus transactions. 2. TMCE BEND H - Must be
low. If asserted by bus, parity, or stack errors, or certain
processor ROM states, the bus cycle will end. 3. UBCC HI BYTE H and
UBCC LO BYTE H - Asserted for all DATAO bus transactions and for
DATAOB transactions coincident with byte address bit BAMX 00. 4.
SSRL PT SEL(1) H - Asserted by any page table address. When the
above conditions are valid, data on PDRB BR(05:00)B L is written into
the selected page table entry when timing pulse SAPC PULSE BC9 H goes
high. This occurs at time T4 of the Pause or Long Pause Cycle. The
contents of a page table entry can be read by selecting the page
table's output on drawing SAPC onto SAPC APR BIT(15:00)H and then on
drawing SSRJ to BUS INTD(15:00)L.
Bits 15 and 14 of each page table entry indicate if any
location of that page have been written into or accessed
respectively. Bit 15 is set if a write cycle occurs during the
access of the associated memory page. Bit 14 will be set on any
access. Once one of these bits has been set, all subsequent accesses
of that page cause the contents of these bits in the entry to be read
out and written back into the memory. Any new information caused by
the current reference in ORed into the bits at this time. Bits are
not set if this reference causes an Abort or if an internal register
is accesed. Both bits are cleared only by writing 0 into them when
writing into that page table entry.
MAP SPACE TABLE
The Map Space Table is shown on drawing SAPD. The space table
has 6 entries, one for each instruction and data space of Kernel,
Supervisor, and User modes. Each entry contains a 6 bit maximum
virtual page field, a transparent bit, and a 2 bit page table number.
The table is contained in an 8X10 bit memory implemented with 4 74170
4X4 register files and 2 9338 8X1 memorys. The write addresses for
all the memory chips are supplied directly from virtual address lines
BAMX(03:01)H and data from the internal bus SAPD BR(09:00)H is
written into the memories when the following conditions are true:
1. SSRL SSR REG(1) H - Asserted when any of the system status
registers or the Map Space Table is addressed on the internal
physical address bus.
2. SAPA WR OK H - Asserted for all DATAOx bus transactions
with BEND off.
3. SAPA HI BYTE BC9 H and SAPA LO BYTE BC9 H - Pulsed at T5
of an internal bus cycle to load the data.
The low order 8 bit's (74170s) read address is multiplexed
from the virtual address BAMX(03:01) for examining the contents of
the tables, and from the mode, SSRB MODE(1:0)H, and space, SSRB I
SPACE, of the current transfer. When reading the contents of the
tables, the data is selected, on drawing SAPC, to SAPC APR BIT(15:00)
and then, on drawing SSRJ to the internal bus, BUS INTD(15:00)L.
The 9338 8 bit memories implementing the page table number
are 3 port memories, two read ports and 1 write port each with
separate address lines. The write port address comes from
BAMX(03:01), for writing data from internal bus bits SAPD BR(09:08).
The write clock conditions are teh same as for the rest of the table.
One read port is used for examining the contents of the table. Its
address is also BAMX(03:01), and its data goes to the APR BIT data
selector. The other read port supplies the page table number. This
address is the processer mode, SSRB MODE(1:0)H, and the
instruction/data space selection, SSRB I SPACE. The data is used as
the high order bits of the address into the page table memories (SAPA
and SAPB) selecting the quadrant of the memory and therefore the
appropriate page table.
PHYSICAL ADDRESS MULTIPLEXER
Refer to drawing SAPJ. The Physical Address Multiplexor
consists of the three 74s157 multiplexer chips, whose enable inputs
are always enabled. The select signal is true when SSRE MAPPING L is
true and SAPD PAGE TRANS H is false, selecting the page table outputs
as the physical address. If MAPPING is false or if the MAP MAP
indicates that this is a Transparent page table, the virtual address
is selected al the physical address. Bits 16 and 17 of the physical
address are supplied in two forms. SAPJ PA(17:16)H are presented to
the Unibus drivers and internal bus devices. During semiconductor
memory references, these bits are inhibited to prevent internal
registers from responding. During unibus cycles when mapping, bits
come from the page table; if not mapping, DAPD EX MEM FLAG H is used.
This forces PA(17:16) to be asserted when BAMX(15:13) are asserrted
indicating an I/O address.
The signal SABJ SM CYC OK L is sent to the semiconductor
memory controler to indicate that this cycle is intended for it and
not for the Unibus.
CONSOLE ADDRESS DISPLAY AND CONTROL
The sources of the Address Display bits SAPK DISP ADR(17:00)H
are shown on drawings SAPH, SAPJ, and SAPK. Address Display bits
SAPK DISP ADR(09:00)H are not affected by the Mapping Box and the
setting of the console Address Display Select switch. The source of
these bits is DAPB BAMX(09:00)H. Address display bits SAPK DISP
ADR(17:10)H depend upon the status of the mapping box, the console
Address Display Select switch position, the console switches, and the
DAPD EX MEM FLAG H signal. The source of SAPK DISP ADR(17:10)H is
summarized in the following table:
Address Display|Mapping|Source of ADDRESS Display Bits
Select Switch |enabled| (17:16) | (15:10) | (09:00)
_______________|_______|___________|___________|___________
PROG PHY | NO |EX MEM FLAG| BAMX | BAMX
PROG PHY | YES | PA | PA | BAMX
CONS PHY | NO | SWR | BAMX | BAMX
CONS PHY | YES | SWR | BAMX | BAMX
KERNEL, I or D | NO | 0 | BAMX | BAMX
SUPER, I or D | | | |
USER, I or D | YES | 0 | BAMX | BAMX
The Console Address Display Select switch performs mode and space
select functions, in addition to ADDRESS dispolay selection. UBCJ
DIS ADRS SEL(2:0)H inputs from the console are decoded by a decoder
(drawing SSRK). The outputs are used with ROM OUT12 to set the
appropriate space control flip-flops under console control conditions
(more on this later).
ABORT CONTROL LOGIC
Drawing SAPL shows the abort detect logic, SSRC the abort
control logic, and SSRD the abort error bits. A memory management
abort causes a processor interrupt that is vectored through Kernel
virtual address location 250 in D space. The abort is caused by one
of three tyypes of illegal memory references. If one of these is
detected by the abort detect logic, the memory reference is not
completed and the processor traps immediately to location 250 in
Kernel D space. The three categories of illegal memory references
are: 1. Page length fault - An access was attempted to a virtual
page larger than that allowed by the Maximum Virtual Page entry for
that space as stored in the Map Space Table. 2. Read fault - A read
access was attempted to a page whose page table entry did not have
the Read Access Bit on. 3. Write fault - A write cycle was
attempted to a page whose page table entry did not have the Write
Access Bit on.
On drawing SAPL, two comparator chips compare the virtual
address, DAPC BAMX(15:10)H with the Maximum Virtual Page entry, SAPD
MAX PAGE (6:1)H. If the virtual address is larger, SAPL LENGTH FAULT
L is asserted.
If SAPB PT12 H, the Read Access bit of the page table is not
asserted, and SAPA C1 B L, false for all read cycles, is not
asserted, SAPL READ FAULT L is asserted.
SAPL WRITE CYCLE H is asserted during DATO, DATOB, and DATIP
cycles. DATIP is included, since it indicates a write is iminent.
If SAPW WRITE CYCLE H is asserted when SAPB PT13 H is not, SAPL WRITE
FAULT L is asserted.
When any of the error conditions are present, SAPL ERROR H
and SAPL ABORT COND H are asserted. SAPL ERROR H goes to the D input
of the INHIBIT flip-flop on drawing SSRK. This flip-flop is clocked
at T4 of the BUST part of every memory cycle that is mapped. The
flip-flop is cleared by either INIT or by diong an examine or deposit
with the console Address Select switch in either "Program Physical"
or "Console Physical" position. Thus, any abort condition asserts
SSRK INHIBIT(1)L which prevents any internal register selection
flip-flop from being clocked. Refer to the internal register control
logic on drawing SSRL. The SSRK INHIBIT flip-flop is required for
proper operation of the internal register logic on SSRL when the RC
processor clock is set very slow for maintence purposes.
When SAPL ABORT COND H is asserted, SSRC ABT FLG(1) is set
and SSRC KT11C ABORT FLAG L is asserted, which causes the processor
to abort the transfer and trap to 250.
UNIBUS ADDRESS DRIVERS
The Unibus A address drivers are shown on drawing SAPK.
These drivers are enabled by the UBCA CPBSY B H signal from the
processor Unibus control logic. The 18 bit Unibus A addres output,
BUSA(17:00)L, is made up of physical address bits SAPJ PA(17:06H and
virtual address bits DAPB BAMX(05:00)H. The mapping logic provides
SAPJ PA(17:06)H.
MAP ROM AND DECODE
The Map ROM includes four 74187 256X4 Read-Only Memories.
The ROM and associated decode logic is shown on drawing SSRA. The
ROM effectively extends the processor ROM width by 16 bits. The Map
logic decodes the ROM output to control the operation of the mapping
box in coincidence with processor control operations. Seven ROM bits
provide separation of I and D space accesses; other ROM bits provide
miscellaneous control.
Each 74187 ROM provides 256 4-bit locations that are
addressed by ROM address bits RACD RAR(07:00)H. The following table
lists the ROM function that is decoded from each ROM output, or
combination of ROM outputs:
ROM OUTPUT | SIGNAL DERIVED |PURPOSE
______________|___________________|__________________________________
ROM OUT(3:1)=0|N/A |No operation.
ROM OUT(3:1)=1|SSRA RESTORE PS(1)H|Forces procesor to restore PS if
| | abort occurs during trap sequence.
ROM OUT(3:1)=2|N/A |Not used.
ROM OUT(3:1)=3|N/A |Not used.
ROM OUT(3:1)=4|SSRA BRK.30 H |Indicates processor is in BRK.30
| | microstate.
ROM OUT(3:1)=5|SSRA JSR.30 |Prevents destruction of processor
| | register contents if an abort
| | occurs during a JSR.
ROM OUT(3:1)=6|SSRA ROM110H |Clears SR(17:16) on SAPK after
| | START or CONTINUE.
ROM OUT(3:1)=7|SSRA CLR PSR(1)H |Clears PS Restore in FET.00 and
| | BRK.00 microstates.
ROM OUT4 |N/A |Not used.
ROM OUT5 |BSOP1 |Bus condition code is Bus Operation 1.
ROM OUT6 |KERNEL DATAI |Bus transaction is Kernel mode DATI.
ROM OUT7 |BUST |Indicates BUST cycle.
ROM OUT8 |I IF MTP SPACE |Forces I space if current instruction
| | is MTPI or MFPI and both the current
| | and previous modes are not both user.
ROM OUT9 |SSRB I SPACE ALWAYS|Forces I SPACE.
ROM OUT10 |N/A |Not used.
ROM OUT11 |I IF PREV=I |Asserts SSRB I SPACE if previous
| | memory cycle was I.
ROM OUT12 |I IF CNSL=I |Asserts SSRB I SPACE if console
| | operation selects I.
ROM OUT13 |I IF SRCF7 |Asserts SSRB I SPACE if instruction
| | is source register 7.
ROM OUT14 |I IF DSTF7∧ |Asserts SSRB I SPACE if instruction
| ¬(MTP+MFP) | is destination register 7 and not
| | MT/MF space.
ROM OUT15 |I IF DSTF7 |Asserts SSRB I SPACE if instruction
| | is destination register 7.
ROM OUT16 |I IF DSTF7∧ |Asserts SSRB I SPACE if instruction
| DSTM2 | is destination register 7 and
| | destination mode 2.
______________|___________________|__________________________________
ROM outputs ROM OUT(3:1) are decoded by a 74s138. The
outputs are clocked in to flip-flops by SSRK PULSE23H, which occurs
near the beginning of every processor microcycle. SSRA RESTORE
PS(1)L is asserted only during processor microstate SVC.60. This is
the Bust part of the push of the old PS onto the stack specified by
the new PS during any trap or interrupt sequence. This signal sets
the PSR flip flop. The PSR flip-flop stays set until SSRA CLR
PSR(1)L is asserted, which occurs during the FET.00 or BRK.00
microstates. Thus, the PSR flip-flop is only set during the push of
the old PS and PC onto the stak during a trap or interrupt. If a
Mapping Box abort occurs during either of these push attempts, the
old PS and PC must be restored. The old PS is temporarialy stored in
the processor BR; the old PC is in the DR. The purpose of SSRA PS
RESTORE(1) is to force the processor through microstates ZAP.10
throuth ZAP.30 and to enable clocking of the PS register in the
processor. Refer to Flow Diagram 12 in the KB11A drawing set. The
old PS is restored to the PS register, and the old PC is restored to
the PC register.
If an abort occurs during a JSR instruction, SSRA JSR.30(1)
asserts SSRA INH PWE (Inhibit Pad Write Enable), which prevents the
processor from writing into the general registers. This function may
be invoked if an abort occurs on the push of the destination register
onto the stack during a JSR (microstate JSR.30) or if an abort occurs
on the fetch of the new top of the stack (MRK.20). At JSR.30 the old
PC is normally written into the destination register thus destroying
the destination register contents. SSRA INH PWE prevents this
destruction. At MRK.20 teh stack pointer, register 6 is normally
modified by N (the MARK argument) + 2. SSRA INH PWE prevents this
modification if an abort occurs at the new top of the stack.
SSRA ROM110H is asserted on a console START or CONTINUE and
is used to clear SR(17:16), on drawing SAPK, in case any console
operations were done that might have set them.
MODE AND SPACE CONTROL
Refer to drawing SSRB. SSRB MODE(1:0)H are loaded from
several sources, depending on different conditions at the beginning
of each Bust cycle. The conditions are as follows:
1. From PDRD PS(15:14) - This is the current mode from the
current Processor Status word. This is the usual mode and
requires that this not be any of the following types of
cycles:
ROM OUT06 - Kernel mode DATI
ROM OUT12 - Console I space
MFP+MTP - Move from/to previous space
ROM OUT05 - Bus operation type 1
2. From SSRK CNSL MODE(1:0) - This is the mode selected from
the consloe panel switch. It is used if ROM OUT12 indicates
that this is a console cycle.
3. From PDRD PS(13:12) - This is the previous mode field from
the current Processor Status word. This input is selected if
this is a move from/to previous space instruction, indicated
by IRCC MFP+MTP, and this is a bus operation type 1 indicated
by ROM OUT05.
The I space decoders assert I SPACE A L or I SPACE B L under
the following conditions
1. SSRA ROM OUT8 - I space is selected if the current
instruction is a move to or from previous I space. IRCA IR
15(1)L ensures D space (MTPD+MFPD).
2. SSRA ROM OUT13 - This output asserts I space if the
current instruction is source register 7 (DPCH SRCF7L
asserted).
3. SSRA ROM OUT14 - This output asserts I space if the
current instruction is destination register 7 (SSRB DSTF7H),
and if teh instruction is not an MTP or MFP instruction.
4. SSRA ROM OUT11 - This output asserts I space if previous
memory reference was I space. It is ANDed with the output of
the PREV=I flip-flop which stores the I space condition form
the previous memory cycle. Used for continuatin of DATAIP
cycles.
5. SSRA ROM OUT15 - This output asserts SSRB I SPACE whenever
the destination register is 7.
6. SSRA ROM OUT12 - This output asserts I space if I space is
selected at eh console control (SAPP CNSL I SPACE H asserted).
7. SSRA ROM OUT16 - This output asserts I space whenever the
destination mode is 2 and the destinatin register is 7. It is
used only for the special Floating Point immediate
constuction.
8. SSRA ROM OUT9 - This ROM output is an unqualified request
for I space. No other conditins are required to assert I
space. Used for instruction fetches.
The I space control logic is required to provide high-speed
memory management throughput because there is a lack of direct
association of I space for each specific microstate. SSRB I SPACE A
L and SSRB I SPACE B L are used to set the I SPACE flip-flop (drawing
SAPD) during T1 of the Bust cycle. This logic minimizes the delay
required to genenrate the most significant bit of the Map Space Table
which indicates which Page Table is to be used.
STATUS REGISTER 0 (SR0)
The contents and format of SR0 are described in the section
on the description of registers. The SR0 bits and control logic
are shown on drawings SSRD, SSRF, and SSRH. The bits are multiplexed
onto the internal bus BUS INTD(15:00)L on drawing SSRJ.
The enable mapping bit and the abort flags are on SSRD. These bits
can be loaded from the internal bus PDRB BR(15:12). The flip-flops
are strobed by SSRK PULSE89 when the following is true:
1. SAPH BAMX(02:01) - Indicating that of the Status registers,
0 is being referenced.
2. UBCC HI BYTE - The high byte is being written.
3. SSRL SSR REG(1) - A Status register address is selected.
4. TMCE C1 H - This is a write cycle.
5. SAPA BEND B L - This is not an early terminated cycle.
The abort flags that show the cause of an abort can be set by their
direct set inputs. The fault detection logic is described above
and showin on drawing SAPL. The fault signal outputs are SAPL READ
FAULT, SAPL READ FAULT, AND SAPL LENGTH FAULT. These inputs are
strobed into the flip flops by the following conditions:
1. SAPA BEND B L - This is not an early teminated cycle.
2. SSRE MAPPING - Mapping is enabled.
3. SSRD NO ERROR(1) - No errors have been detected on previous memory
references.
4. SSRL INT REG - The current memory reference is not accessing an
internal register.
If these conditions are true the data is strobed into the direct
set inputs of the flip-flops by PULSE BC89 clock pulse that occurs
during the processor Pause cycle. The contents of SR0(14::12) are
ORed to the data input of the NO ERROR flip-flop, which is clocked
by the SSRK BC910 clock pulse. If no error flags are set, the NO
ERROR flip-flop will remain set.
The PC MODE(1:0) flip-flops (on drawing SSRH) are loaded
from the current processor mode at the beginning of each instruction
fetch. The clock input, SSRF NEW SEQUENCE, is produced by RACA UIRK
or the BRK.30 signal decoded at the ROM output. Clocking is inhibited
by SSRD NO ERROR going false, so the mode of the failing PC is retained.
The ERROR MODE(1:0) and the ERROR IN I SPACE flip-flops (on
drawing SSRF) are loaded with the current processor mode and the I
space condition, at the beginning of each bus cycle. Clocking
is inhibited by SSRD NO ERROR going false, so the mode and space of
the failing address is retained.
STATUS REGISTER 1 (SR1)
Status Register 1, shown on drawing SSRF, is loaded with the
virtual address of the current bus cycle SAPH VA(15:00) at the beginning
of each bus cycle. Clocking is inhibited by SSRD NO ERROR going false,
so the virtual address that caused the abort is retained. SR1 is read
through the internal bus multiplexor onto BUS INTD(15:00) on drawing
SSRJ.
STATUS REGISTER 2 (SR2)
Status Register 2, shown on drawing SSRH, is loaded with the
virtual address of the current bus cycle, SAPH VA(15:00) at the beginning
of each instruction fetch. Clocking is inhibited by SSRD NO ERROR
going false, so the virtual address of the instruction that caused
the abort is retained. SR2 is read through the internal bus multiplexor
onto BUS INTD(15:00) on drawing SSRJ.
INTERNAL DATA BUS MULTIPLEXERS
The internal data bus multipoexers are made up of eight 74153
multiplexers, shown on drawing SSRJ. The multiplexers are capable
of selecting the contents of one of four registers as thh 16-bit output to
the processor internal data bus. The inputs are the APR, SR0, SR1, or
SR2. The APR can be either the Page Tables or the Map Space Table,
depending on the input selected by the APR read multiplexer on drawing
SAPC. The specific register selected is determined by decoding virtual
address bits BAMX(04:01), the SSRL SSR REG flip-flop, and the SSRL APR
REG flip-flop. The input selection logic decodes this information
(see drawing SSRL) as indicated in the following table: